1. Field of the Invention
The invention relates to the field of floating gate memory devices particularly those fabricated with metal-oxide-semiconductor technology.
2. Prior Art
For many years now, metal-oxide-semiconductor (MOS) technology has been used to fabricate electrically programmable read-only memories (EPROMs). Many of these cells employ floating gates, that is, generally polysilicon members completely surrounded by an insulator. Electrical charge is transferred into the floating gate through a variety of mechanisms such as avalanche injection, channel injection, Fowler-Nordheim tunnelling, hot electron injection from the substrate, etc. Commercial EPROMs with floating gates first used avalanche injection to charge the floating gate; in second generation memories (and most current floating gate EPROM memories) channel injection is used for programming. These memories are erased by exposure to ultraviolet radiation.
Commercial electrically programmable and electrically erasable memories (EEPROMs) generally use a thin oxide region to tunnel charge into and from a floating gate. In a typical memory, a two transistor cell is used. See, for instance, U.S. Pat. No. 4,203,158 for a discussion of such cells and U.S. Pat. No. 4,266,283 for a discussion of related circuitry. These cells do not as readily lend themselves to reduced geometries as do the EPROM cells. Thus, while relatively dense EPROMs are currently available (e.g., 256K) the EEPROMs are not widely available in capacities above 64K.
More recently, the technology for developing a flash EPROM has become known. These memories employ cells which are more like EPROM cells in overall structure. Erasing occurs in some cases by tunnelling charge from the floating gate to the channel region through the gate oxide layer. Flash EPROM cells and a method for fabricating them are disclosed in a co-pending application entitled LOW VOLTAGE EEPROM CELL, Ser. No. 892,446, filed Aug. 4, 1986 and assigned to the assignee of the present application.
The flash EPROM cells described in the above application may be fabricated in very high density since there is only a single device per cell. With these cells erasing occurs in blocks that is, by way of example, all the cells in the array are simultaneously erased. In contrast, the EEPROM cells described in U.S. Pat. No. 4,203,158 have the advantage that individual cells, or small groups of cells, can be separately erased. (In both memories each cell or small group of cells can be separately programmed.) These cells however, use two devices per cell and hence can not be fabricated in as high a density as the flash EPROM cells described in the above mentioned application.
In some cases it is desirable to have both flash EPROM cells and the individually erasable EEPROM cells on the same substrate. In a microprocessor, for instance, a program may be stored in flash EPROM cells. There may be certain data such as constants which needs to be periodically changed. The individually erasable EEPROM cells are ideal for this type of data. (The term individually erasable EEPROM cell is also meant to include a small group of such cells which are erased together such as eight cells storing a digital word.) Generally, the number of individually erasable EEPROM cells needed is small compared to the number of flash EPROM cells and hence there is a large saving in substrate area if the program is stored in the flash EPROM cells and the number of individually erasable EEPROM cells are kept to a minimum.
The present invention describes processing which permits the simultaneous fabrication of the individually erasable EEPROM cells such as described in U.S. Pat. No. 4,203,158 and the flash EPROM cells described in the above mentioned application. No additional masking steps or other processing steps other than those used to fabricate the flash EPROM cells are used to simultaneously fabricate the individually erasable EEPROM cells.
The present invention makes use of lateral diffusion in the substrate to form regions under a polysilicon member. Lateral diffusion is well-known in the prior art and in some prior art processing has been put to advantage. For example, the lateral diffusion of oxygen ions to form a buried oxide region is described in European Patent Office Publication No. 0164281 published on Dec. 11, 1985. The Applicant does not know of any prior art, however, where lateral diffusion has been used to form regions for the tunnelling of charge such as described in the present application.